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ordering number : enn * 6614 82500rm (ot) no. 6614-1/12 functions cd-rom decoder/encoder functions cd decoder/encoder functions pit and wobble clv servo cav audio functions scsi interface (include the register block) subcode encoder/decoder functions atip demodulator/atip decoder write strategy function (cd-r/rw) cd-dsp function with built-in digital servo features ecc and edc correction/addition (decoding/encoding) for cd-rom data. ecc error correction/addition (decoding/encoding) for subcode data servo control implemented in a digital servo system (decoding/encoding) wobble clv servo control using atip data (encoding) atip decoding function and crc check function (decoding/encoding) circ code generation and addition and efm modulation (encoding) cav audio functions write strategy function supports 8 and 16 recording. built-in scsi interface (supports ultra scsi) supports 40 decoding and 16 encoding. clock frequencies: cd-rom block: 33.8688 mhz, scsi block: 20 mhz ultra scsi data transfer rate: 20 mbyte/s (maximum synchronous transfer rate), fast scsi: 10 mbyte/s (maximum synchronous transfer rate), 5 mbyte/s (maximum asynchronous transfer rate) uses 16-bit data bus 50 ns edo dram. from 1 to 64 mbits of buffer ram can be used. (16-bit data bus edo dram) the user can freely set up the cd main channel, c2 flag, and subcode areas in buffer ram. batch transfer function (function for transferring the cd main channel, c2 flag, subcode, and other data in a single operation) multi-transfer function (function for automatically transferring multiple blocks to the host in a single operation) package dimensions unit: mm 3210-sqfp208 28.0 (3.2) 30.6 0.15 0.2 0.35 3.8max 0.5 30.6 (0.5) (1.25) 28.0 1 52 156 105 53 208 104 157 preliminary sanyo: sqfp208 [LC898023K] LC898023K sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan 40 playback/16 write cd-r/rw encoder/decoder ic with built-in scsi interface cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. ?urn-proof?stands for proof against buffer under run error, not for proof against burning. ?urn-proof?is a trademark of sanyo electric co.,ltd.
no. 6614-2/12 LC898023K parameter symbol conditions ratings unit supply voltage v dd 5 max ta 25? ?.3 to +6.0 v v dd 3 max ta 25? ?.3 to +4.6 v i/o voltages v i 5, v o 5 ta 25? ?.3 to v dd 5 + 0.3 v v i 3, v o 3 ta 25? ?.3 to v dd 3 + 0.3 v allowable power dissipation pd max ta 70? 750 mw operating temperature topr ?0 to +70 ? storage temperature tstg ?5 to +125 ? soldering conditions (pins only) 10 seconds 260 ? specifications absolute maximum ratings at v ss = 0 v parameter symbol conditions ratings unit min typ max [i/o cells, 5.0 v power supply] supply voltage v dd 5 4.5 5.0 5.5 v input voltage range v in 0v dd 5v [internal cells, 3.3 v power supply] supply voltage v dd 3 3.0 3.3 3.6 v input voltage range v in 0v dd 3v allowable operating ranges at ta = ?0 to +70?, v ss = 0 v parameter symbol conditions ratings unit min typ max high-level input voltage v ih ttl level inputs: (2), (14) 2.2 v low-level input voltage v il 0.8 v high-level input voltage v ih ttl level inputs with built-in pull-up resistors: (13) 2.2 v low-level input voltage v il 0.8 v high-level input voltage v ih ttl level schmitt trigger inputs: (1) 2.5 v low-level input voltage v il 0.6 v high-level input voltage v ih (15) 2.0 v low-level input voltage v il 0.8 v high-level input voltage v ih cmos level schmitt trigger inputs: (3) 0.8 v dd v low-level input voltage v il 0.2 v dd v high-level input voltage v ih cmos level inputs with built-in pull-up resistors: (4) 0.7 v dd v low-level input voltage v il 0.3 v dd v analog input voltage v ani (5) 1/4 v dd 3/4 v dd v high-level output voltage v oh i oh = ?2 ma: (8) v dd ?2.1 v low-level output voltage v ol i ol = 12 ma: (8) 0.4 v high-level output voltage v oh i oh = ? ma: (7) v dd ?2.1 v low-level output voltage v ol i ol = 8 ma: (7) 0.4 v high-level output voltage v oh i oh = ? ma: (6), (13), (14) v dd ?2.1 v low-level output voltage v ol i ol = 2 ma: (6), (13), (14) 0.4 v low-level output voltage v ol i ol = 48 ma: (15) 0.4 v low-level output voltage v ol i ol = 8 ma: (12) 0.4 v low-level output voltage v ol i ol = 1 ma: (9) 0.4 v high-level output voltage v oh i oh = ? ma: (11) v dd ?2.1 v low-level output voltage v ol i ol = 4 ma: (11) 0.4 v analog output voltage v ano (10) 1/4 v dd 3/4 v dd v input leakage current i il v i = v ss , v dd : (1), (2), (14), (15) ?0 +10 ? output leakage current i oz in the high-impedance output state: (9), (11), (12) ?0 +10 ? pull-up resistance r up (12), (13) 40 80 160 k pull-up resistance r up (4) 50 100 200 k electrical characteristics at ta = ?0 to +70?, v ss = 0 v, v dd = 4.5 to 5.5 v the applicable pin groups are listed on the following page.
applicable pins [input] (1) ??????wobble, cs, rd, wr, def, hfl, tes (2) ??????sua0 to sua7, test0 to test4, reset (3) ??????write (4) ??????fg (5) ?????ad0, ad1, rrec, fe, te, vref, fr, opp, jitin, pckistf, pckistp, efmin, efmin2, slcist1, slcist2 [output] (6) ??????ldon (7) ?????efmg, shock, lock, efmo, ssp2/1, rapc, wapc, h11to, ldh, atest3, atest1, wdat, nwdat (8) ??????pck2, ra0 to ra9, cas0 to cas1, ras0 to ras2, lwe, uwe, oe, subsync (9) ??????pds1 to pds3 (10) ?????da0 to da2, tdo, fdo, sldo, spdo, jitc, lout, rout, pdo, rpo, sldo, slco1 to slco3 (11) ?????dslb (12) ?????int0, int1, swait [inout] (13) ?????d0 to d7, id0 to id15 (14) ?????atipsync, biclk, bidata, acrcng (15) ?????ack, atn, bsy, c/d, db0 to db7, dbp, i/o, msg, req, rst, sel note: the xtal0, xtal1, xtalck0, and xtalck1 are not included in the dc characteristics. scsi pin input characteristics active negation output characteristics note: the active negation output characteristics only applies to db0 to db7, req, and dbpb rise time test circuit no. 6614-3/12 LC898023K scsi driver tp 47 ? 5% 15pf 5% 2.5v + a13188 parameter symbol conditions ratings unit min typ max input threshold voltage v t + t1 v dd = 4.50 to 5.50 v 1.60 2.00 v v t ?t1 v dd = 4.50 to 5.50 v 0.80 1.10 v hysteresis width ? v tt1 v dd = 5.0 v 0.41 0.5 parameter symbol conditions ratings unit min typ max output high voltage v oh 2.5 v output low voltage v ol 0.4 v
no. 6614-4/12 LC898023K de-scramble & buffering address generator microcontroller ram access address generator address generator ecc & edc scsi i/f block address generator data output input i/f bus arbiter & dram controller external buffer dram each block bus control signal each block register r0-r87 cd-dsp i/f & sync detector digital servo & circ endec host micro controller decoder pll & clock generator *8 dac *9 test0 to 4 *13 *10 *6 *7 *3 *2 cav-audio sub-code ecc address generator *1 write strategy & link-position *12 sub-code i/f de-interleve/interleve address generator atip/clv servo atipsync int0, int1 swait xtalck0 xtal0 xtalck1 xtal1 each block scsi block data bus[0:7] address bus[0:21] ram data bus[0:15] LC898023K a13191 *1 dslb (pin96) to fr (pin123), ad0 (pin127) to spdo (pin142), shock (pin147) to pck2 (pin155) *2 subsync *3 db0 to db7, dbp, bsy, msg, sel, rst, req, i/o, c/d, ack, atn *6 rd, wr, sua0 to sua7, cs *7 d0 to d7 *8 io0 to io15 *9 ra0 to ra9, ras0, ras1, ras2, cas0, cas1, oe, uwe, lwe *10 wobble, bidata, biclk *12 write, ssp2/1, rapc, wapc, h11t0, ldh, test2/1, wdat, nwdat, efmg *13 lout, rout block diagram
pin functions no. 6614-5/12 LC898023K pin type i input b bidirectional pin nc not connected o output p power supply a analog pin pin no. pin name type pin function 1v ss p digital system ground (v ss ) 2 ra4 o 3 ra5 o 4 ra6 o cd-rom encoder/decoder dram address lines 5 ra7 o 6 ra8 o 7 ra9 o 8v dd p digital system power supply (5 v) 9v ss p digital system ground (v ss ) 10 io0 b 11 io1 b 12 io2 b cd-rom encoder/decoder buffer ram data lines 13 io3 b these pins have built-in pull-up resistors. 14 io4 b 15 io5 b 16 v dd p digital system power supply (3.3 v) 17 v ss p digital system ground (v ss ) 18 io6 b 19 io7 b cd-rom encoder/decoder buffer ram data lines 20 io8 b these pins have built-in pull-up resistors. 21 io9 b 22 io10 b 23 v ss p digital system ground (v ss ) 24 v dd p digital system power supply (3.3 v) 25 io11 b 26 io12 b 27 io13 b cd-rom encoder/decoder buffer ram data lines 28 io14 b 29 io15 b 30 atipsync i atip sync detection signal 31 bidata b 32 biclk b atip demodulator i/o signals 33 wobble i 34 v dd p digital system power supply (5 v) 35 v ss p digital system ground (v ss ) 36 acrcng o atip crc error signal 37 write i write strategy signal control input 38 ssp2 o servo sampling pulse output 39 ssp1 o servo sampling pulse output 40 rapc o laser control sampling pulse output 41 wapc o laser control sampling pulse output 42 h11t0 o running opc sampling pulse continued on next page.
no. 6614-6/12 LC898023K continued from preceding page. pin no. pin name type pin function 43 ldh o recording laser diode control signal output 44 v dd p digital system power supply (3.3 v) 45 v ss p digital system ground (v ss ) 46 atest3 o analog block test output 47 atest1 o analog block test output 48 wdat o recording laser diode control signal output 49 nwdat o recording laser diode control signal output (wdat inverted) 50 v dd p analog system power supply (3.3 v) 51 v ss p analog system ground (v ss ) 52 v dd p digital system power supply (5 v) 53 v ss p digital system ground (v ss ) 54 r1 i 55 vcnt1 i write strategy analog signals 56 mdc1 i 57 pd1 o 58 swait o wait signal to the microcontroller 59 int0 o interrupt request signal outputs to the microcontroller 60 int1 o these are open-drain outputs with built-in pull-up resistors. 61 d0 b 62 d1 b 63 d2 b microcontroller data signal lines 64 d3 b these pins have built-in pull-up resistors. 65 d4 b 66 d5 b 67 d6 b 68 v dd p digital system power supply (5 v) 69 v ss p digital system ground (v ss ) 70 d7 b microcontroller data signal line 71 sua0 i 72 sua1 i 73 sua2 i 74 sua3 i command register selection address 75 sua4 i 76 sua5 i 77 sua6 i 78 sua7 i 79 cs i chip select signal input from the microcontroller 80 rd i data read signal from the microcontroller 81 wr i data write signal from the microcontroller 82 test0 i test pin. this pin must be tied to v ss . 83 vcnt i vco control voltage 84 r i vco bias resistor connection 85 pd o charge pump output 86 v dd p analog system power supply (3.3 v) 87 v ss p analog system ground (v ss ) 88 test1 i test pin. this pin must be tied to v ss . 89 reset i reset input 90 xtalck0 i crystal oscillator circuit input (33.8688 mhz) continued on next page.
no. 6614-7/12 LC898023K continued from preceding page. pin no. pin name type pin function 91 xtal0 o crystal oscillator circuit output 92 rout o d/a converter output 93 v ss p analog system ground (v ss ) 94 v dd p analog system power supply (5 v) 95 lout o d/a converter output 96 dslb o slc pwm output 97 slcist1 i efm slice level setting input 98 slcist2 i 99 v ss p analog system ground (v ss ) 100 v dd p analog system power supply (3.3 v) 101 slco0 o 102 slco1 o efm slice level output 103 slco2 o 104 v dd p digital system power supply (5 v) 105 v ss p digital system ground (v ss ) 106 slco3 o efm slice level output 107 efmin i efm input 108 efmin2 i 109 test4 i test pin. this pin must be tied to v ss . 110 jitc o jitter output 111 rpo o p/n balance adjustment 112 opp i 113 pckistf i frequency comparator charge pump 114 pckistp i phase comparator charge pump 115 v ss p analog system ground (v ss ) 116 v dd p analog system power supply (3.3 v) 117 pdo o charge pump filter 118 pds1 o charge pump selection 119 pds2 o 120 v dd p digital system power supply (3.3 v) 121 v ss p digital system ground (v ss ) 122 pds3 o charge pump selection 123 fr i vco frequency setting 124 test2 i test pin. this pin must be tied to v ss . 125 test3 i test pin. this pin must be tied to v ss . 126 c ss i center servo input pin 127 ad0 i ad input 128 rrec i optical signal discrimination input 129 fe i fe input 130 te i te input 131 vref i vref input 132 ad1 i ad input 133 v ss p analog system ground (v ss ) 134 da0 o da output 135 da1 o da output 136 da2 o da output 137 tdo o tracking output continued on next page.
no. 6614-8/12 LC898023K continued from preceding page. pin no. pin name type pin function 138 v dd p analog system power supply (5 v) 139 v ss p analog system ground (v ss ) 140 fdo o focus output 141 sldo o sled output 142 spdo o spindle output 143 v ss p digital system ground (v ss ) 144 v dd p digital system power supply (3.3 v) 145 subsync o subcode sync signal 146 efmg o efm gate signal 147 shock o shock detection signal output 148 lock o pll lock state output 149 def i defect detection signal input 150 hfl i mirror detection signal input 151 tes i tes comparator input 152 efmo o post-binarization efm signal output 153 ldon o laser control 154 fg i fg input 155 pck2 o pck output 156 v dd p digital system power supply (5 v) 157 v ss p digital system ground (v ss ) 158 xtalck1 i scsi interface crystal oscillator circuit input (20 mhz) 159 xtal1 o scsi interface crystal oscillator circuit output 160 db0 b scsi connection 161 v ss p digital system ground (v ss ) 162 db1 b scsi connection 163 db2 b 164 v dd p digital system power supply (5 v) 165 db3 b scsi connection 166 db4 b 167 v ss p digital system ground (v ss ) 168 db5 b 169 db6 b scsi connection 170 db7 b 171 v ss p digital system ground (v ss ) 172 v dd p digital system power supply (5 v) 173 v ss p digital system ground (v ss ) 174 dbp b 175 atn b scsi connection 176 bsy b 177 v ss p digital system ground (v ss ) 178 ack b scsi connection 179 rst b 180 v dd p digital system power supply (5 v) 181 msg b scsi connection 182 sel b 183 v ss p digital system ground (v ss ) 184 c/d b scsi connection continued on next page.
no. 6614-9/12 LC898023K continued from preceding page. pin no. pin name type pin function 185 v ss p digital system ground (v ss ) 186 v dd p digital system power supply (5 v) 187 req b scsi connections 188 i/o b 189 v ss p digital system ground (v ss ) 190 v dd p digital system power supply (3.3 v) 191 v ss p digital system ground (v ss ) 192 nc unused 193 nc unused 194 ras0 o 195 ras1 o dram ras signal outputs 196 ras2 o 197 lwe o dram lower write enable 198 v dd p digital system power supply (3.3 v) 199 v ss p digital system ground (v ss ) 200 uwe o dram upper write enable 201 cas0 o dram cas signal output 202 cas1 o 203 oe o dram output enable 204 ra0 o 205 ra1 o cd-rom encoder/decoder dram address lines 206 ra2 o 207 ra3 o 208 v dd p digital system power supply (3.3 v) pin functions bsy, ack, msg, sel, req, atn, rst, i/o, c/d (input/output) scis bus control. db0 to db7, dbp (input/output) scsi data bus. cs (input) chip select signal from the microcontroller. the microcontroller interface is active when this pin is low. rd, wr (input) connect the microcontroller read and write lines to these inputs. swait (input) wait signal output to the microcontroller. when accessing buffer ram, the microcontroller must wait if this pin is low. sua0 to sua7 (input) internal register address lines d0 to d7 (input) microcontroller data bus. these pins have built-in pull-up resistors. int0, int1 (output) interrupt request signals output to the microcontroller. int1 can be set to output the atapi interrupt by setting int1en (conf-r11 bit 7) these are open drain outputs with built-in 80 k (at room temperature, 5 v) pull-up resistors. i/o0 to i/o15 (input/output) buffer ram data bus. these pins have built-in pull-up resistors. ra0 to ra9 (output) buffer ram address lines.
ras0, ras1, ras2 (output) buffer dram ras outputs. normally, ras0 is used. however, if two 16-mbit drams are used, connect the ras0 and ras1 lines to the ras pins on the drams. if four 16-mbit drams are used, connect the ras0, ras1, ras2, and lwe lines to the ras pins on the drams. cas0, cas1 (output) buffer dram cas outputs. normally, cas0 is used. however, if two 16-mbit drams are used, connect the cas0 output to the cas pins on the drams. if 2-cas type drams are used, connect cas0 to ucas and cas1 to lcas. oe (output) buffer ram read output. uwe, lwe (output) buffer ram write outputs. connect these to the corresponding pins. if 2-cas type drams are used, uwe must be connected. (leave lwe open.) 1. analog interface pins rrec (input) optical discrimination input. fe (input) focus error signal input. te (input) tracking error signal input. vref (input) input for the servo system reference voltage. ad0, ad1, ad2 (input) a/d converter auxiliary inputs. da0, da1, da2 (input) d/a converter auxiliary inputs. tes (input) tes comparator input. tdo (output) tracking control signal output. fdo (output) focus control signal output. sldo (output) sled control signal output. spdo (output) spindle control signal output. 2. efm input block pins efmin (input) efm signal input. the high-frequency components of the rf signal acquired from the rf amplifier are cut with a capacitor, and this pin inputs that signal biased by the value of the slco0 to slco3 outputs passed through a low-pass filter. efmin2 (input) used to change the time constant of the low-pass filter. slcist1, slcist2 (input) slice level controller charge pump bias resistor connection. slco0, slco1, slco2, slco3 (output) slice level controller charge pump outputs. these levels bias the rf signal input to the efmin pin after being passed through a low-pass filter. dslb (output) slice level control pwm output. efmo (output) post-binarization efm signal output. (for monitoring) no. 6614-10/12 LC898023K
3. efm clock generation block pins fr (input) efm reproduction pll vco bias resistor connection. pdo, pds1, pds2, pds3 (output) efm reproduction pll lag-lead filter connection. pckistf (input) efm reproduction pll frequency comparator charge pump bias resistor connection. pckistp (input) efm reproduction pll phase comparator charge pump bias resistor connection. rpo (output) p/n balance adjustment. opp (input) p/n balance adjustment. pck2 (output) efm reproduction bit clock output. 4. jitter discrimination pins jitc (output) jitter output. 5. spindle speed detection pins fg (input) input for the speed monitor signal from the spindle driver. 6. audio interface pins lout, rout (output) left and right channel audio signal outputs. 7. rf amplifier interface pins ldon (output) rf amplifier interface. 8. write strategy pins write, ssp2/1, rapc, wapc, h11t0, ldh, atest3, 1, wdat, nwdat (i/o) write strategy signal connections. 9. atip decoder related pins atipsync (output) atip synchronization detection signal. (for monitoring) bidata, biclk (i/o) input mode: input of the biphase data and biphase clock when an external atip demodulator is used. output mode: output of the biphase data and biphase clock when the internal atip demodulator is used. (for monitoring) wobble (input) wobble signal is input when the internal atip demodulator is used. acrcng (output) outputs the result of the atip decoder crc check. (for monitoring) no. 6614-11/12 LC898023K
ps no. 6614-12/12 LC898023K reset (input) the LC898023K reset input. a low level input resets the LC898023K. this pin must be held low for at least 1 ? when power is first applied. test4 to test0 (input) test inputs. these pins must be connected to ground. xtalck0 (input), xtal0 (output) drive these pins at 33.8688 mhz. this signal is used, without modification, as main clock for the cd-rom encoder and decoder blocks, including the dram interface. xtalck1 (input), xtal1 (output) main clock for the scsi block. the LC898023K is designed so that it can operate even when the ecc and scsi blocks are not synchronized. providing a 20 mhz input to the xtalck0 and xtalck1 pins assures that correct, synchronized transfer at 10 mbyte/s (20 mbyte/s for ultra scsi) can be achieved. the maximum frequency that can be used is 20 mhz. since both edges of the clock signal are used by ultra scsi, the duty ratio must be correct. add feedback resistors on the xtalck1 and xtal1 pins and take other measures as required. r, vcnt, pdo, r1, vcnt1, pd1, mdc1 (i/o) clock reproduction pll circuit pins. subsync (output) subcode sync output signal from the circ encoder during recording. (for monitoring) efmg (output) outputs a high level during recording. shock (output) outputs a high level when a mechanical shock is detected. lock (output) outputs a high level when the pll circuit is locked. def (input) inputs the defect detection signal. hfl (input) inputs the mirror detection signal. this catalog provides information as of august, 2000. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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